1. Technical Field
Analog to digital converters (ADC) are disclosed and, more specifically, configurations and timings of the input stages of ADCs are disclosed.
2. Description of the Related Art
In all ADC architectures, an input signal is sampled at defined timed intervals and converted into a time discrete representation with finite resolution. This function consists of two operations called sampling and quantization. In the sampling operation, the input signal is sampled at a defined point in time, and the value of the input signal for that point in time is stored for further processing. The sampling operation is very critical as all errors introduced limit the accuracy that can be obtained for the total system.
For many ADC architectures like pipelined ADCs and successive approximation ADCs, the input signal is sampled at the input stage of the ADC while the quantization function is distributed across the complete converter.
The sampling function is very often performed by dedicated circuitry called sample-and-hold (SHA) or track-and-hold (THA) amplifiers in order to optimize performance. However, such functions tend to consume a significant amount of power since the requirement to performance in this first block is high.
In order to simplify the system and reduce power dissipation, several solutions exist to combine the SHA with the input stage of the ADC itself. The following description assumes a pipelined ADC implemented with a switched capacitor technique, even though the solutions will be applicable for other ADC architectures, stand alone THAs and SHAs as well.
An explanation of the principle of a sampling switch can be found in FIG. 1. The sampling block usually consists of a capacitor 100 that is connected to the input signal during part of clock period and disconnected from the input signal during the rest of the period. The clock signal controls the switch 101. During the high phase, S, of the clock signal, the switch is closed and the input is connected to the sampling capacitor 100. At the high to low transition of the clock signal, the switch is opened and the value of the input signal at that point in time is stored on the capacitor until the next time the switch is closed.
An implementation of such a principle consists of significantly more circuitry even though the basic operation of a sampling switch always follows the principle shown in FIG. 1. In solutions where the SHA is combined with other circuitry inside the ADC, the charge on the capacitor is often changed during the hold period, H. In this period the stored value of the input signal is used for further processing to perform the quantization.
A common problem in sampling switches in general, and in particular in the situations where the charge stored on the capacitor is changed, is the kick-back into the input network that arises when the switch 101 is closed again for a new sampling period. Assuming a dynamic input signal to the sampling switch, the voltage across the capacitor will be equal to the input signal at the falling edge of the clock signal. During the hold phase, the voltage across the capacitor will be kept unchanged, or it will be altered by other circuitry. The input signal will during the same period change to a different value. When the switch is closed again, a transient current will be pulled from the input signal in order to charge the capacitor. This transient current represents noise that is kicked back into the input signal source. The ability of the input signal source to supply the required current to charge the sampling capacitor, and the speed that can be obtained in this process, determines the accuracy in the sample and hold process.
Two major solutions have been used in previous art to reduce the requirements to the input signal driver.
One solution consists of adding a buffer amplifier on-chip right before the sampling switch. This buffer amplifier is designed with sufficient speed to charge the sampling capacitor to the required accuracy in the available time. The kick-back from the capacitor will then be attenuated by this buffer, and the input signal driver will therefore not be exposed to the large transient currents. This solution is not optimum from a noise perspective due to the extra buffer added into the signal path. This buffer will increase the total noise, increase power dissipation, and hence reduce the performance of the system.
Another solution consists of resetting the charge on the capacitor to a fixed value before each time the capacitor is connected to the input signal. This will not remove the transient current kick-back into the input signal source. But as the kick-back is equal for each clock period, it can be shown that the resulting errors are less visible in the ADC output spectrum, and reduced requirements to the input signal source can be accepted.
In order to allow for the resetting function, an extra phase must be introduced into the timing sequence of the SHA. FIG. 2 shows the principle and the timing required to perform such a resetting function.
An extra switch 102 is added to discharge the sampling capacitor prior to each sampling period. This switch is closed when the reset waveform shows a high value. The sequence of operation is as follows.
The switches 101 and 102 are open in the hold phase, and the voltage across the capacitor is used by other circuitry for further processing. This further processing operation must be finished before the reset signal goes high and the reset Switch 102 is closed discharging the sampling capacitor to zero voltage. The switch 102 is then opened while 101 is closed and the sampling capacitor is charged to the voltage of the input signal. The input voltage is then sampled and held across the sampling capacitor at the time the clock signal goes low and switch 101 is opened again. The sampling capacitor could be charged to a different potential than zero voltage. But in practice it is common to discharge it to obtain a voltage as close to zero as possible at the beginning of the sampling period.
The major disadvantage with this kind of resetting scheme is that the total time available for the sampling and hold periods is reduced since a third phase is introduced into the timing sequence. Typically, the reset phase is made at the cost of a shorter sampling phase while the hold phase is kept unchanged. This is still challenging to make work in practice since the total time for reset and sampling becomes short. A short sampling time would require higher driving strength in the external amplifier driving the input signal. This would increase the power dissipation of this amplifier. A shorter hold period would require higher speed, and hence increased power dissipation, in the sensing circuitry used for further processing of the sampled voltage.